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ADVANCE INFORMATION
Data Sheet No. PD60164A
IR1110
SOFT START CONTROLLER IC
Features Product Summary
VDDS/VSS ISS/IDD DC bus registration response time +/- 5V +/- 5mA 100msec (typ.)
* Self-contained soft charging of DC bus capacitor * DC bus voltage regulation * 3-phase or 1-phase AC input * Applicable to 115/230/380/460/575V AC input * Drives SCR phase controlled half bridge * Programmable ramp rate * Protection against DC bus short circuit * Fast power dip ride through with automatic ramp back * Selectable shutdown on single phase loss * 1-phase and 3-phase loss fault output * Insensitive to phase rotation * High line or low line fault output * Low power consumption * Integrated watchdog function for each phase * 64-pin MQFP package
Min. DC bus regulation 35% of VDCMAX voltage with capacitive load Programmable DC bus ramp time 100msec to 330msec (typ.)
Typical Application
* * * *
Motor drives Welders Battery chargers Power supplies
Description
The IR1110 is a high performance analog IC designed to control ramp rate and voltage of the DC bus from either single or three phase AC line voltage input. It controls a SCR half bridge and provides robust ride through capability in event of transient loss of line, and DC bus regulation with eternal reference input. Comprehensive line status fault output including 1/3 phase loss and high or low line fault provides versatile line diagnostic capability to the system. The IR1110 is based on advanced low power design so it can utilize the SCR snubber derived power supply.
Package
64 Lead MQFP
System Block Diagram
Snubber and Snubber derived power supply
IR1110
and Peripheral Components
(Optional)
+
AC 3-Phase Input
(Optional)
-
IR1110
ADVANCE INFORMATION
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to AGND and DGND, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VDD VSS VIN VBIN VLED VLNSET ILED RthJA TA TJ TS TL
Definition
Positive supply voltage Negative supply voltage Operating input voltage range on UIN,VIN & WIN pins Operating input voltage on VBOS and VBNEG Operating input voltage on 1PHLED, LNLED, and LNLSLED pins Operating input voltage on LNSET Sinking current on 1PHLED, LNLED, and LNLSLED pins Thermal resistance, junction to ambient Operating ambient temperature Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-- -- (VSS + 0.4) - 4.5 -- -- -- -- -40 -- -55 --
Max.
6.0 -6.0 (V DD - 0.4) 3.0 VDD (VDD - 0.4) 3 60 85 150 150 300
Units
V
mA C/W
C
Recommended Component Values
All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended components specified below.
Symbol
QU QV QW RU1 RV1 RW1 RB RU2 RV2 RW2 RERR RCLAMP1 RCLAMP2 RRAMP
Definition
Phase U/V/W complementary MOSFET
Typ.
IRF7509
Tolerance Units
Comments
Complementary NMOS/PMOS Driver
Resistor divider for input voltage
3.4 X VACrms max
1% .25W 1% 1%
k
Note 1
Bias resistor Resistor divider for input voltage
249k 9.09k
DC bus regulation error resistor Ramp clamp resistor 1 Ramp clamp resistor 2 Ramp resistor 2M 430k 100k 82k 5% 5% 5% 5%
2
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ADVANCE INFORMATION
IR1110
Recommended Operating Conditions cont.
All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended components specified below.
Symbol
RPKLL1 RPKLL2 RDIP1 RDIP2 RDFIL RPKD RPKFIL RPOS1 RNEG1 RPOS2 RNEG2 RWDU RWDV RWDW RLS1 RLS2 RSG1 RSG2 RINTU RINTV RINTW RINTRU RINTRV RINTRW RLED1 RLED2 RU, RV, RW RGU RGV RGW RDU RDV RDW
Definition
Line voltage peak holding resistor 1 Line voltage peak holding resistor 2 Voltage dip resistor 1 Voltage dip resistor 2 Voltage dip filter resistor Timing wave peak voltage discharge resistor Timing wave peak voltage filter resistor Resistor divider for DC bus voltage input Feedback resistor for DC bus voltage Amp Resistor divider for DC bus voltage Phase U/V/W watchdog resistor
Typ.
2.2M 6.8M 332k 1.0M 15k 1M 56k 3.2 X VACrmsmax 9.09k 9.09k 845k
Tolerance Units
5% 5% 1% 1% 5% 5% 5% 1% .5W 1% 1% 1% k
Comments
Note 1,2
Note 3
Line fault output reference divider resistor 1 Line fault output reference divider resistor 2 SCR firing anode voltage reference resistor 1 SCR firing anode voltage reference resistor 2 Phase U/V/W integrator resistor
357k 78.7k 0.82k X VACrmsmax 10k 1M
1% 1% 1% 1% 1% Note 4
Phase U/V/W integrator reset resistor 33.2k 1%
LNLSLED pin resistor for opto interface LNLED pin resistor for opto interface Phase U/V/W SCR driver pull-up resistor Phase U/V/W SCR driver output resistor
6.2k 6.2k 5.6k 33
5% 5% 5% 5% .25W
Phase U/V/W SCR driver filter resistor
470
5% .
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IR1110
ADVANCE INFORMATION
Recommended Operating Conditions cont.
All capacitors are rated 6.3V unless otherwise specified. All resistors are rated 1/16W unless otherwise specified. The typical connection diagram is shown in figure 3. For proper operation the device should be used with the recommended componens specified below.
Symbol
CUVLO C1PH C3PH CERR CRAMP CPKLL CBDIP1 CBDIP2 CHOLD CPK CWDU CWDV CWDW CINTU CINTV CINTW CU, CV, C W DRAMP
Definition
Capacitor on UVLOCAP pin Capacitor on 1PHCAP pin Capacitor on 3PHCAP pin Capacitor on DCREGC pin Capacitor on CRAMP pin Capacitor on VPKLL pin Capacitor on BDIP1 Capacitor on BDIP2 Capacitor on BDIPHLD Capacitor on VPK Capacitor on WDCAPU, WDCAPV, and WDCAPW Capacitor between CINTU/V/W and INTNU/V/W Capacitor in SCR driver circuit Diode in series with RRAMP
Typ.
.1 .001 .022 .22 1.0 .1 3300 1000 .33 .33 .027
Tolerance Units
5% 5% 5% 10% 10% 10% 5% 5% 10% 10% 2% F PF F
Comments
.0082
2%
.0047/25V IN4148 HCPL0701
10%
Opto1,Opto2 Fault output opto couplers
Note 1) Power rating is based on 550VAC rms maximum. For lower AC line voltage, power can be reduced proportionally. Vac rms max = Maximum operating RMS value of AC line voltage. Use the nearest standard 1% value to calculated value. Resistor must be rated for peak line voltage. Note 2) RPOS2 is not required if no series inductor(s) in place on positive DC bus. Resistor must be rated for peak line voltage. Note 3) VDD = 5.0V2.5%. If 5.1V2% zener diode sets VDD, use 866k 1%. Note 4) With these values LNLED is used for low line detection and is low at line voltage greater than approximately 57% of Vacrms maximum voltage. Note 5) Use the nearest standard 1% value to calculated value. Note 6) CRAMP and RRAMP sets the bus voltage ranp-up time. Minimum value of CRAMP is 0.68F, maximum value is 3.3F. See Operation Description - Ramp Circuit.
Special Mode of Operation
1. Dedicated single phase operation
For operation with a one-phase bridge, connect 1PHSEL (pin12) to VSS. Use the U and V inputs. Connect WIN (pin3) to ground. Use the SCRU (pin47) and SCRV (pin46) outputs. Use RPKD = 3.0M, RWDU, RWDV = 1.0M , CINTU,CINTV = 0.0068F 2%. The following components can be omitted: RW1, RW2, RWDW, CWDW, RINTW, RINTRW, CINTW.
2. Operation without DC bus voltage regulation
For operation without bus voltage, ie. maximum DC bus voltage only, connect VBREF (pin8) to VSS. RERR and CERR can be omitted. Connect DCREGC (pin10) to ground.
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ADVANCE INFORMATION
IR1110
DC Electrical Characteristics
RBIAS = 249K/1%, VDD = 5.1V, VSS = 5.1V and TA = 25C unless otherwise specified.
Symbol
VDD VSS IDD ISS VIN VBREF VIL1 VIH1 VPCINT VPCR+ VPCRI1PHCAP+ I1PHCAPI3PHCAP+ I3PHCAPVOLLED VOH LED UVLO IUVLO+ VHSCR VLSCR VRAMPBUF RVBREF IBDIPCAP VtLNLED+ VtLNLEDVtLNLS Vt1PH
Definition
Positive Supply Voltage Negative Supply Voltage VDD Supply Current VSS Supply Current Input Voltage Range for UIN, VIN, and WIN Input Voltage Range for VBREF Input logic low voltage on 1PHEN, LNLSSL Input logic high voltage on 1PHEN, LNLSSL Positive Output Voltage Swing at CINTU, CINTV, and CINTW Pins Positive Output Voltage Swing at CRAMP Pin Negative Output Voltage Swing at CRAMP Pin Sourcing Current at 1PHCAP pin Sinking Current at 1PHCAP pin Sourcing Current at 3PHCAP pin Sinking Current at 3PHCAP pin Output Low Voltage at 1PHLED, LNLSLED, and LNLED pins Output High Voltage at 1PHLED, LNLSLED, and LNLSLED pin Undervoltage lockout between VDD-GND Sinking Current at UVLOCAP pin Output Voltage at High level at SCRU, SCRV, and SCRW pins Output Voltage at Low level at SCRU, SCRV, and SCRW pins Output Voltage at VRAMP pin Input Resistance On VBREF pin Sourcing Current of BDIPCAP pin Peak threshold voltage on UIN/VIN/WIN pins for LNLED to switch low Peak threshold voltage on UIN/VIN/WIN pins for LNLED to switch high Peak threshold voltage on UIN/VIN/WIN pins for LNLSLED to stay low Peak threshold voltage on UIN/VIN/WIN pins for 1PHLED to stay low
Min. Typ. Max. Units Test Conditions
4.8 -4.8 ----1.5 0 --2.2 ----0 --------0 VDD 0.4 4.1 60 ----------2.2 2.0 ----4.4 86 4.5 0.1 4.0 400 5 2.3 2.1 .5 .5 4.6 110 --0.31 ------2.4 2.2 --V --k uA BDIPCAP=VSS VLNSET = 1.0V Note 2 All input voltages present All input voltages present V uA VUVLOCAP=VDD IO = 1mA IO = -1mA 5.1 -5.1 3.0 -3.0 --------4.0 4.0 --2.0 5.0 3.0 15.0 0.12 --5.6 -5.6 6.0 -5.0 4.0 5.0 -2.0 --4.5 4.5 ----------.4 VDD V A 1PHCAP=VSS 1PHCAP=GND 3PHCAP=VSS 3PHCAP=GND Output sinking current = 3.0mA Output sourcing current = 3mA V Peak voltage of Vin = 4.0V Note 1 mA V Note 3 Note 3 Note 4 Note 4
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IR1110
ADVANCE INFORMATION
Notes for DC Electrical Characteristics
Note 1) VBREF=5.0V will assure full SCR firing on to produce the maximum amount of DC bus voltage and faster convergence to the maximum DC bus voltage. Although VBREF=4.0V corresponds to the maximum voltage, it will take longer time to converge to the maximum DC bus voltage. Note 2) These voltage values are linearly proportional to VLNSET. For example, if VLNSET = 2.0V, then all values are twice of those values listed in the table. Note 3) VDD must be regulated within 2.5%. VSS must be regulated within 5%.
AC Electrical Characteristics
VDD = 5.1V, VSS, = 5.1V, CL = 1000pF and TA = 25C unless otherwise specified.
Symbol
tr tf tWSCR tDLL
Definition
Turn-on rise time on SCRU, SCRV, and SCRW Turn-off fall time on SCRU, SCRV, and SCRW Output pulse width of SCRU,SCRV, and SCRW LNLSLED propagation delay
Min. Typ. Max. Units Test Conditions
--------500 500 15 30 --------ns s LNLSSL=VDD, C3PH =.022uF, (note 1)
tD1PH tLN tS1PH
1PHLED propagation delay LNLED propagation delay Shutdown time after loss of single phase
-------
8.3 150 15
----20
ms ms
C1PH = .001uF (note 2) 1PHEN = VDD, CUVLO = .1mF, C1PH = .001mF, (note 3)
tfFO tW1PH tUVLCK tRAMP VENSCR PPUBAL
Fall time from high to low on LNLSLED, 1PHLED, LNLED 1PHLED pulse width Power up UVLOCK delay DC bus ramp time Minimum input voltage on UIN, VIN, and WIN for enabling SCR firing Phase-to-phase unbalance between pulses on SCRU, SCRV, and SCRW
-----
50 2 60 150
-----
ns
Pull-up resistor = 6.2kW C1PH =.001mF, (note 4)
msec
CUVLCK=.1uF, (note 5) CRAMP=1uF, RRAMP=82k,(note 6)
-----
RU2/RU1 --X 12 1.5 3 ---
V
(note 7) Firing angle = 90
o
Notes 8 and 9 Firing angle = 140 Note 9
---
---
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ADVANCE INFORMATION
IR1110
Notes for AC Electrical Characteristics
Note 1) Delay is proportional to the capacitor values with minimum allowed value of C 3PH = .01F Note 2) Depends on CPKLL charge condition Note 3) CUVLO = .1F, C1PH = .001F. Increasing CUVLO increases the delay/response time of the 1phase lockout. Note 4) Pulse width is proportional to C1PH. Maximum allowed values of C1PH is .001F. Note 5) Power up delay is set by CUVLO or by VDD rise time whichever takes longer. In this condition, VDD rise time must not be less than 100msec, and 1-phase shutdown must be enabled. If this is less than 100msec or 1-phase shut down is disabled, CUVLO must be increased to 0.22F in order to increase the undervoltage lockout time to greater than 100msec. See Note 3) above on additional effect of increasing CUVLO. Note 6) Ramp time is proportional to the capacitor value. Note 7) This value corresponds approximately to 15V minimum SCR firing voltage. For 15V minimum SCR firing voltage, (RSG2/RSG1) X VDD = (RU2/RU1) X 15. Note 8) PPUBAL applies to steady operation, is deviation of any firing point to closest balanced set of firing points. Note 9) Firing angle is defined with respect to zero delay (ie. max output voltage.
System Operating Characteristics and Specifications
All peripheral component values are those listed in the recommended operating condition unless otherwise specified.
Symbol
VAC
Definition
Line-to-line AC voltage range (1%)
Min. Typ. Max. Units Test Conditions
80 161 322 120 230 460 50/60 --2 100 150 140 276 552 63 99.8 ------Hz % % msec msec VRMS
Ru1,Rv1,Rw1=475K RPOS1 ,RNEG1=453K Ru1 ,Rv1,Rw19537K RPOS1 ,RNEG1=887K Ru1,Rv1,Rw1=2X953K RPOS1 ,RNEG1=887K
fLINE VBRANGE VBREG VBRES tRAMP1
Input line frequency DC bus voltage controllable range DC bus voltage regulation DC bus voltage step response time DC bus voltage ramp up time at power up
47 35 ------
VBREF=1.4V to 4V VBUS=35% to 100% Note 6 CRAMP = 1F RRAMP = 82k (Note 7) CRAMP = 1 F RRAMP = 82k (Note 7) CRAMP = 1 F CUVLO = 0.1F Note 9) Voltage drop below the reference voltage at BDIP2 pin Figure 2, Note 14 1PHEN = VDD 1PHEN = VDD
tRAMP2
DC bus voltage ramp up time at power dip ride through Power up delay time before ramp up
---
75
---
msec
tdPWR
---
190
---
msec
tdDIP1
Delay time to start ramp-up after recovery from a transient loss of line voltage Firing angle range Delay time to shutdown SCR firing pulses after loss of one phase input Delay time to start ramp-up after recovery from a loss of one phase input 1.5 15 ---
15
msec
aFIRE td1PHS td1PHE
----30
160 30 ---
msec msec
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IR1110
ADVANCE INFORMATION
System Operating Characteristics and Specifications
All peripheral component values are those listed in the recommended operating condition unless otherwise specified. td1FIRE First SCR firing angle at ramp-up -- 20 32 CRAMP=1F, RRAMP = 82k (Note 10) CRAMP=2.2 F, RRAMP = 47k (Note 10) CRAMP=3.3 F, RRAMP = 30k (Notes10,12, 13) CRAMP = 1F, RRAMP = 82k CRAMP=3.3F, RRAMP = 30k (Notes 11 and 13)
16
25
14
22
RLIMFIRE
Rate of advance of firing angle from last max firing angle during ramp-up
---
10 7
20 14
Notes for System Operating Characteristics
Note 6) Step change of VBREF may result in excessive bus capacitor charging current. Rate of change of VBREF should be decreased in order to limit bus capacitor charging current for practical application. Note 7) Time to ramp up to 99.8% DC bus level at a power up. It does not include the power up delay time. The practical limitation of the minimum time (50msec) depends on the inrush current to the DC bus capacitor. Ramp time is proportional to CRAMP. Note 8) Time to ramp back to 99.8% DC bus level from 50% DC bus level at a momentary power dip. This does not include the delay time to start ramp-up (tDDIP) Note 9) The value depends on CUVLCK Note 10) The value depends on CRAMP, RPK, RRAMP Note 11) The value depends on CRAMP Note 12) See operation description - Ramp Circuit Note 13) Firing angle defined with respect to fully off (zero output voltage) firing angle. Note 14) Firing angle defined with respect to zero delay.
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ADVANCE INFORMATION
IR1110
Operating Mode/Fault Output Matrix Chart
Mode Fault Fault output condition indicator
Nonmultiplexed Normal Multiplexed SCR output firing active. LNLSLED = low, 1PHLED = high SCR output firing disabled for period of loss. LNLSLED = high, 1PHLED = high SCR output firing disabled for period of loss. LNLSLED = high, 1PHLED = high (Note 1)
Description
SCR output firing active. LNLSLED = low, 1PHLED = high
External setting
LNLSSL = VDD 1PHEN = VDD or VSS 1PHSEL = VDD LNLSSL = VSS 1PHEN =VDD or VSS 1PHSEL = VDD LNLSSL = VDD 1PHEN =VDD or VSS 1PHSEL = VDD LNLSSL = VSS 1PHEN =VDD or VSS 1PHSEL = VDD LNLSSL = VDD 1PHEN = VSS 1PHSEL = VDD LNLSSL = VSS 1PHEN = VSS 1PHSEL = VDD LNLSSL = VDD 1PHEN = VDD 1PHSEL = VDD LNLSSL = VSS 1PHEN = VDD 1PHSEL = VDD
3-phase loss
Nonmultiplexed Multiplexed
3-phase Input operation uld tical is
1-phase loss without shutdown
Nonmultiplexed Multiplexed
1-phase loss with shutdown
Nonmultiplexed Multiplexed
High/Low AC line
LNLED
Nonmultiplexed 1-phase loss Multiplexed
1-phase input operation
Nonmultiplexed Normal Multiplexed
High/Low AC line
LNLED
SCR output firing active. LNLSLED = low, 1PHLED = toggles low for 2msec once or twice per line cycle SCR output firing active.LNLSLED toggles high while 1PHLED toggles low for 2msec once or twice per line cycle. (Note 2) SCR output firing disabled for period of loss. LNLSLED = low, 1PHLED = toggles low for 2msec once or twice per line cycle SCR output firing disabled for period of loss. LNLSLED toggles high while 1PHLED toggles low for 2msec once or twice per line cycle. (Note 2) If line voltage exceeds the specified level on LNSET=desired voltage, LNSET voltage, then LNLED = low. Otherwise 1PHEN =VDD or VSS LNLED = high 1PHSEL = VDD SCR output firing disabled for period of loss. LNLSSL = VDD LNLSLED = high, 1PHLED = high 1PHEN =VDD or VSS 1PHSEL = VSS SCR output firing disabled for period of loss. LNLSSL = VSS LNLSLED = high, 1PHLED = high 1PHEN =VDD or VSS 1PHSEL = VSS SCR output firing active. LNLSLED = low. LNLSSL = VDD 1PHLED toggles low for 2msec once or twice 1PHEN =VDD or VSS per line cycle 1PHSEL = VSS SCR output firing active. LNLSLED toggles LNLSSL = VSS high while 1PHLED toggles low for 2msec 1PHEN =VDD or VSS once or twice per line cycle. (N ote 2) 1PHSEL = VSS If line voltage exceeds the specified level on LNSET=desired voltage, LNSET voltage, then LNLED = low. Otherwise 1PHSEL= VSS LNLED = high 1PHEN =VDD or VSS
Note 1) LNLSLED may toggle high once for 2msec after event of phase loss. Note 2) 1PHLED and LNLSLED are completely synchronized and complementary.
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IR1110
Functional Block Diagram
ADVANCE INFORMATION
3
Firing voltage reference
COMP
3 3
COMP
LINE VOLTAGE
3
Line Voltage Processing
3
Line Sync & Timing wave generator Timing wave Watchdog
SCR FIRING PULSES
Single Phase
Phase Loss Detect
High/Low Line Fault + -
Line Loss
Ramp Clamp Amp ENABLE
Ramp Generator
Timing wave Reference Generator
VBUS
Vbus Dip Detector
RESET
VBUS REF
+
Error Amp
1+s
1
Figure 1
Firing Angle,=
Vin
Figure 2
applied volts*seconds
<0>
time
10
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ADVANCE INFORMATION
IR1110
Typical Connection Diagram
+15V
CU RDU RGU QU RGV QV RU CV RDV RGW QW RLED2 RLED1 RWDU RWDV RSG2 RLS1 RV CW RDW RW OPTO1 OPTO2
VDD
CWDV CWDU RLS2 CPK C W D WR P K F I L RPKD
To SCRs
AVSS
VDD
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDD
RSG1
TEST2
TEST1
SCRU
VPKDISC1
WDCAPU
WDCAPV
LNLED
SCRW
WDCAPW
SCRREF
DGND
DVDD
SCRV
1PHLED
LNLSLED
LNSET
VPKREC
VPK
33
RWDW
VDD
CINTW RINTW
52 53 54 55 RINTRW 56 CINTV RINTV 59 RINTRV 60 CINTW RINTW 61 62 63 RINTRW 64 57 58
AVDD CINTW INTNW RINTW RSTRW CINTV INTNV RINTV RSTRV CINTU INTNU
32 31 30
VINTDISC2 DVSS
RDIP1 CHOLD
BDIPHLD BDIP1 BDIPCAP
29 RDFIL 28 27 26 25 RPKLL1 24 23 22 RB 21 RRAMP 20 CRAMP RPKLL2 DRAMP CPKLL CUVLO CBDIP2 CBDIP1 RDIP2
IR1110
MQFP64 Non Square
BDIP2 AGND AGND UVLOCAP VPKLL RBIAS
DCREGC
DCREG2
DCREG1
LNLSSL
1PHCAP
3PHCAP
VBAMPP
VBAMPN
1PHSEL
VBUSO
VBREF
1PHEN
AVSS
WIN
AVDD
VRAMP
18
RINTU RSTRU
1 UIN
RRAMP CRAMP RAMPERR
VIN
10
11
12
13
14
15
16
17
RU1
U V W DCDC+
RV1 RW1 RNEG1 RPOS1 RU2 RW2 RV2 RNEG2 RPOS2
RCLAMP1
VDD VBUS REF
RERR
C1PH
19
2
3
4
5
6
7
8
9
C3PH RCLAMP2
VDD
VSS
CERR
Figure 3
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IR1110
Lead Definitions
Symbol
DVDD DGND DVSS AVDD AGND AVSS UIN/VIN/WIN VBAMPP VBAMPN VBUSO VBREF DCREG2 DCREG1 DCREGC 1PHSEL 1PHEN LNLSSL 1PHCAP 3PHCAP VRAMP RAMPERR CRAMP RRAMP RBIAS VPKLL UVLOCAP BDIP1 BDIP2 BDIPHLD BDIPCAP VPKDISC1 VPKDISC2 VPK VPKREC WDCAPU/V/W LNSET LNLSLED 1PHLED LNLED CINTU/V/W INTNU/V/W RINTU/V/W RSTRU/V/W SCRU/V/W TEST1 TEST2 SCRREF
ADVANCE INFORMATION
Pin #
44 43 31 17 25,26,43 4,31,51 1,2,3 5 6 7 8 9 11 10 12 13 14 15 16 18 19 20 21 22 23 24 29 27 30 28 33 32 34 35 38,37,36 39 40 41 42 61,57,53 62,58,54 63,59,55 64,60,56 47,46,45 48 49 50
Description
Logic positive supply voltage. Logic ground Logic negative supply voltage Analog positive supply voltage Analog ground Analog negative supply voltage Phase U/V/W voltage inputs DC bus OP Amp. positive input, connect to DC bus(-) via resistor DC bus OP Amp. negative input, connect to DC bus (+) via resistor DC bus OP Amp. output DC bus regulation voltage reference input DC bus error amplifier output via series diode DC bus error amplifier output DC bus error compensation (External capacitor connection pin) Single phase input mode select. Note 1) on page 12 Single phase shutdown mode enable. Note 2) on page 12 Phase loss Fault Output Select. Note 3) on page 12 Single phase loss detect timing capacitor Three phase loss detect timing capacitor Buffered voltage ramp circuit output Ramp error amplifier input Ramp timing capacitor Ramp timing resistor Bias current resistor Line-to-line peak voltage holding capacitor Under voltage lockout delay capacitor DC bus voltage dip detection 1 DC bus voltage dip detection 2 DC bus voltage dip hold capacitor DC bus voltage dip timing capacitor Line synchronization timing wave peak voltage discharging resistor No connection Line synchronization timing wave peak voltage Line synchronization timing waveform Watchdog timing capacitor for phase U, V, and W Line voltage comparator reference input Line Loss Fault Output Single Phase Loss Fault Output High/Low line status Output Phase U/V/W integral amplifier output Phase U/V/W integral amplifier negative input Phase U/V/W integral amplifier resistor connection Phase U/V/W integral discharge resistor Phase U/V/W SCR gate signal Test purpose pin (Should be tied to VDD) Test purpose pin (No connection should be made) SCR gate signal reference
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ADVANCE INFORMATION
IR1110
Lead Definitions
Note 1) 1PHSEL = VDD for 3 phase operation, 1PHSEL = VSS for 1 phase operation. See Operating Mode/Fault Output Matrix Chart for the detail. Note 2) 1PHEN = VDD for enable, 1PHEN = VSS for disable. See Operating Mode/Fault Output Matrix Chart for the detail. Note 3) LNLSSL = VDD for total line loss only, LNLSSL = VSS for multiplexing total line loss/1 phase loss. See Operating Mode/Fault Output Matrix Chart for the detail.
Package Dimensions - 64 Lead MQFP
01-2023
01
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IR1110
ADVANCE INFORMATION
Operation Description
Overall Functional Diagram A detailed functional diagram of the IR1110 and peripheral components is shown in Figure 4. The IR1110 receives signals from the AC input lines U, V, W, and DC bus voltage, DC+, DC-, via resistor dividers, and delivers line-synchronized pulses SCRU, SCRV, SCRW to external SCR gate driver circuits. The timing of these pulses controls the DC bus voltage. The IR1110 also delivers Status Feedback signals, that denote loss of all input phases, loss of one input phase and low/high AC line voltage. The "ground" of the IR1110 is common with the SCR cathodes. Line Voltage Processing circuit The inputs to the line voltage processing circuit represent the voltage across the SCRs. Each of the three outputs of this circuit, RINTU, RINTV, RINTW is a voltage waveform that is negative over the range of control of firing angle of the associated SCR, and positive outside this range. The possible portion only of these waveforms appears at RSTRU, RSTRV, RSTRW. Timing Wave Integrators Each Timing Wave Integrator integrates the negative portions of the output waveforms of the Line Voltage Processing circuit, via RINT, and the positive portions, via RINT and RINTR in parallel. The outputs, CINTU, CINTV, CINTW are a set of line synchronized "sawtooth" timing waves. These have the desired phase relationship to the line voltages, so that intersection of these waves with the Timing Wave Reference defines the SCR firing instants. See Figure 5. VPKL-L Store Voltages UIN-VIN, VIN-WIN, WIN-UIN are rectified and the peak value, proportional to the peak line voltage, is stored on CPKLL. The time constant of RPKLL1 and RPKLL2 with CPKLL allows VPLL to track changes of line voltage that take place over a number of cycles, while maintaining an essentially smooth waveform. Watchdog The watchdog resets the Timing Wave Integrator within a few milliseconds of the normal reset point, should an abnormality in the line voltage waveshapes, such as one or all input phases missing, prevent resetting at the normal time. In the normal operation, the watchdog circuit plays only a passive role.
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ADVANCE INFORMATION
IR1110
VPK Store CPK stores a voltage, VPK, that is essentially equal to the peak of the timing waves. RPKD is normally connected to ground via Q1. The time constant of RPKD with CPK allows VPK to track changes of amplitude of the timing waves that take place over a number of cycles, while maintaining an essentially smooth waveform. Ramp Circuit The current source, IRAMP, creates an increasing voltage, VRAMP, across CRAMP, whenever Q3 has been conducting, then switches OFF. The maximum value of VRAMP is clamped at VPK. VRAMP controls the ramp-up rate of the bus voltage. RRAMP shapes VRAMP to a parabolic form, which gives an approximately linear rise of DC bus voltage with a capacitive load. The rate of change of VRAMP at the start of the ramp is set by CRAMP. RRAMP also has some influence on the initial rate of change, but more influence later during the ramp-up period. The greater the initial rate of rise of VRAMP, the greater the maximum first firing angle. Typical relationships between CRAMP,RRAMP,tDPWR, tRAMP1, and tD1FIRE are as follows: CRAMP uF 0.68 1 2.2 3.3 RRAMP k 130 82 47 30 tDPWR (typical) msec 165 190 230 270 tRAMP (typical) msec 100 150 220 330 tD1FIRE (max) degrees 35 32 25 22
The minimum and maximum permissible values of CRAMP are 0.68uF and 3.3uF respectively. Total ramp-up time can be increased above the values shown by increasing RRAMP. For example, with CRAMP=3.3uF and RRAMP open, ramp-up time increases to about 1.2 seconds. The maximum first firing angle is specified at maximum AC input voltage, and assumes that worst case cumulative tolerances of the governing external components cause sufficient phase-to-phase unbalance that firing on one phase only occurs during the early part of ramp-up. The circuit in Figure 15(a) will reduce the maximum first firing angle to 17, if desired. If the voltage regulation function is not used, and the circuit of Figure 13 is not used, the Figure 15(b) circuit can be used in place of the Figure 15(a) circuit for the same purpose. With either circuit, both tDPWR and tRAMP will increase to about 400msec. Ramp Clamp Circuit When Q4 is OFF, the ramp clamp is enabled, and Q3 is controlled by the output of the Ramp Error Amplifier. This amplifier compares |VBUSO|, via RCLAMP1, with VRAMP, via RCLAMP2. The amplified output drives Q3 in a linear mode, diverting IRAMP from CRAMP and forcing VRAMP to be essentially equal to VBUSO x RCLAMP2/RCLAMP1. www.irf.com 15
IR1110
ADVANCE INFORMATION
During transient line voltage outage, the Ramp Clamp is enabled. VRAMP is then forced into the above relationship with VBUSO. The amplitude of VRAMP is thereby preset when the line voltage returns, so that the bus voltage ramps back without significant delay, but also without unacceptable jump of bus voltage. The choice of RCLAMP2/RCLAMP1 is a compromise between the delay in starting ramp-back of the output voltage, and the initial jump of voltage when the line voltage returns after outage. With an inductive filter at the output of the rectifier, RCLAMP2/RCLAMP1 can be set to a higher value than with just a bus capacitor, to minimize the response time in restoring the DC bus voltage after line outage. Timing Wave Reference Summing Amplifier The output of the Timing Wave Reference Summing Amplifier is the Timing Wave Reference; this is essentially the difference between VPK and VRAMP, so long as the output of Error Amplifier 2 is zero. Thus, when VRAMP is zero, the Timing Wave Reference voltage is essentially equal to VPK, and SCR firing angle is close to the zero crossing of the line-to-line voltage; as the ramp increases, the firing angle advances. Refer to Figure 5. Closed Loop Bus Voltage Regulation The bus voltage reference, -VBUSREF, sets the amplitude of the steady bus voltage. This external reference is negative with respect to "ground", i.e., with respect to the positive output terminal of the rectifier bridge. This facilitates derivation of VBUSREF, if required, via a level shift circuit that is referenced to the negative DC bus. If bus voltage control is not used, and steady operation at the maximum DC bus voltage only is required, VBUSREF should be connected to VSS. The Inverting Amplifier inverts the reference to +VBUSREF. If the maximum possible value of |VBUSO| is less than |VBUSREF|, the voltage regulation loop is inactive. The average output of Error Amplifier 1 is always negative, the voltage across CERR is clamped to zero by the parallel diode, the output of Error Amplifier 2 is always zero, and the bus voltage ramps to the maximum possible value. If |VBUSO| becomes greater than |VBUSREF|, the average output of Error Amplifier 1 becomes positive. This output is filtered by RERR and CERR, and a smooth voltage representing the dc error between |VBUSO| and |VBUSREF| appears across CERR. This voltage is amplified by Error Amplifier 2, and fed as an input to the Timing Wave Reference Summing Amplifier. The added input to the Timing Wave Reference Summing Amplifier increases the Timing Wave Reference, delaying the SCR firing angle, and forcing the bus voltage to a value proportional to |VBUSREF|. Since the voltage regulation circuit becomes active only when |VBUSO| exceeds |VBUSREF|, the ramp rate during power-up of the bus voltage is determined solely by the rate of increase of VRAMP. If |VBUSO| starts to exceed |VBUSREF| during ramp up, the output of Error Amplifier 2 starts to oppose the increasing ramp voltage, restraining further increase of bus voltage. Some overshoot occurs while the ramp continues to increase to VPK. In normal operation, after ramp up, the bus voltage is no longer controlled by the ramp, unless an event occurs that causes the ramp to be clamped. Rise and fall rates of the bus voltage that are driven by changes in |VBUSREF| in normal operation are determined by the applied rise and fall rates of |VBUSREF|, and by the characteristics www.irf.com 16
ADVANCE INFORMATION
IR1110
of the load connected to the DC bus. The rate of increase of applied |VBUSREF| should be limited if necessary, to limit the bus capacitor charging current. Adjustment of DC loop gain The voltage regulation loop may exhibit uneven firing angle from one SCR to the next, with loads which have unusually high ripple voltage. Such ripple instability, if it occurs, can be corrected by reducing the DC loop gain. Figure 6 shows how this is done with a voltage divider, R1 and R2, in the voltage regulation loop. SCR Timing Comparators Each SCR Timing Comparator delivers a high output whenever the Timing Wave is instantaneously greater than the Timing Wave Reference. The leading edge is the demanded initiation point for the SCR firing pulse. The duration of the output pulse of the SCR timing comparator is generally much longer than needed to fire the SCR, because the Timing Wave remains higher than the Timing Wave Reference for a significant portion, if not all, of the total cycle time. See Figure 5. SCR Voltage Comparators Each SCR Voltage Comparator compares the instantaneous anode-cathode voltage of the SCR with a fixed reference, SCRREF, which is set by RSG1 and RSG2. This reference is set to represent an actual anode-cathode voltage of about 15V, before attenuation through the input divider resistors. When the instantaneous SCR anode voltage is greater than 15V, the output of the SCR Voltage comparator is high. The outputs of the SCR Voltage and Timing Comparators are ANDed to obtain the output SCR timing pulses, SCRU, SCRV, SCRW. The SCRU, SCRV, SCRW output pulses are thus controlled so that; a) they do not occur when the Timing Wave is less than the Timing Wave Reference b) they do not occur unless the instantaneous SCR voltage is at least 15V positive c) they are terminated when the instantaneous anode-cathode voltage falls below 15V; -i.e. as soon as the SCR turns on With discontinuous output current, more than one firing pulse per cycle for each SCR may be generated. The pulse width of SCRU, SCRV, SCRW is about 6usec at maximum output voltage, and about 13usec at reduced output voltage. SCR Gate Drivers The SCR gate driver circuit, shown in Figure 7, amplifies and stretches the SCRU, SCRV, SCRW timing pulses. C1 and R2 stretch the duration of the output pulse to 60-80usec. This is generally necessary to ensure reliable SCR turn-on. C2 and R4 provide an initial peak turn-on firing current of about .45A, decaying to about .2A within 5usec. The maximum average current consumed by the three SCR driver circuits is about 10mA. If C2 and R4 are omitted, the peak firing current will be reduced to about .2A. R3 can be decreased to say 33W, to restore the peak firing current to .45A; the maximum average supply current will now increase to about 20mA. www.irf.com 17
IR1110
ADVANCE INFORMATION
Voltage Dip Circuit The DC bus voltage will fall if the input line voltage dips or is lost. For short period outage, the bus capacitor voltage may hold up sufficiently that ramp back when the line voltage returns is unnecessary. If the bus voltage falls below a preset level, then the ramp is automatically clamped, in order to avoid an unacceptable jump of bus voltage when the line returns. The Voltage Dip Comparator monitors dips on the DC bus voltage. The bus voltage, VBUSO, is captured on CHOLD. The Voltage Dip Comparator compares a fraction of this captured voltage, with -VBUSO. In normal operation, |kVBUSO| is less than |VBUSO|, and the output of the Voltage Dip Comparator is high. When a short line outage occurs, the voltage captured on CHOLD remains substantially equal to the pre-dip value, while |VBUSO| starts to decrease as the bus capacitor discharges. If |VBUSO| dips to less than k x VBUS1, where VBUS1 is the initial bus voltage, the output of the Voltage Dip Comparator latches low, Q4 is switched off and the ramp is clamped. Q5 is turned ON, discharging the voltage on CERR. RDIP2 kVBUS1 = RDIP1 + RDIP2 where VLLMAX is the maximum design value of rms line voltage x VBUS1 - (0.1 VLLMAX)
The Voltage Dip Comparator remains low for a minimum period, TDELAY2, of approxmately 5 milliseconds, set by CBDIP1. Thereafter, so long as the line voltage is absent or remains abnormally low, the output of the Timing Wave Intersect Comparator remains low, keeping the Voltage Dip Comparator latched low. TDELAY2 in milliseconds is approximately equal to (.0015 X CBDIP1 pF). Thus for CBDIP1 = 3300pF, TDELAY2 is about 5 milliseconds. The total delay, TDELAY_TOT, between the point of initiation of the line voltage outage, and the point at which the voltage dip comparator is allowed to reset, must be at least 10 milliseconds. TDELAY_TOT is the sum of TDELAY1 and TDELAY2. TDELAY1 is the time between the point of initiation of the line outage, and the point at which the bus voltage falls to kVBUS1. Thus, with TDELAY2 set at 5 milliseconds, the minimum allowed value for TDELAY1 is 5 milliseconds. If the bus capacitor is sized so that, at maximum DC load current, the bus voltage will fall to kVBUS1 in less than 5 milliseconds, then CBDIP1 should be increased to ensure that TDELAY_TOT cannot fall below 10 milliseconds. If CBDIP1 is increased so that TDELAY2 is at least 10 milliseconds, TDELAY_TOT will always be greater than 10 milliseconds. This is an inherently safe design approach, though it does add a few milliseconds of potentially unnecessary delay, before ramp-back can commence during a short line outage.
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ADVANCE INFORMATION
IR1110
After the above delay, the Voltage Dip Comparator is reset when the output of the Timing Wave Intersect Comparator goes high, which occurs when the line voltage returns to normal. Q2 is momentarily turned ON, allowing the voltage on CHOLD to reset. Q4 is turned ON, unclamping the Ramp, and Q5 is turned OFF, unclamping CERR. Ramp-back of the bus voltage now occurs. When the output of the Voltage Dip Comparator is low, Q1 is turned OFF. RPKD is then disconnected from ground, allowing CPK to hold its charge during the voltage dip. Voltage Dip during Dynamic Regulation If |VBREF| is rapidly decreased by a sufficient amount, this may cause a decrease of bus voltage that will set the Voltage Dip Comparator and cause the bus voltage to undershoot. Since the timing waves are still present, the output of the Timing Wave Intersect Comparator remains high, and the Voltage Dip Comparator will be quickly reset, ramping the bus voltage back to the set value. This undershoot of the bus voltage will be avoided if changes in |VBUSREF| are controlled at a rate that does not significantly "overtake" the discharge rate of CHOLD, which is set by CHOLD, RDIP1 and RDIP2. Undervoltage and Undervoltage Lockout Comparators The UV Comparator delivers a high output when VDD exceeds the internally fixed reference value. The UV Lockout Comparator delivers a high output when the voltage CUVLO exceeds a nominal value of about 1.5V. CUVLO is driven from a current source of approximately 2uA. The outputs of the UV and UV Lockout Comparators are ANDed. When the output of either comparator is low, the SCR firing pulses are inhibited, and Q4 is turned OFF, clamping the ramp. One Phase Loss Circuit A train of fixed duration (nominal 2msec) pulses are delivered to the gate of Q6, if one input phase is missing. With 1-phase shutdown enabled, each 1-phase loss pulse discharges CUVLO by about 1.5V. During the third successive pulse, CUVLO is discharged sufficiently that the output of the UV Lockout Comparator goes low. The principle of generation of the 1-phase loss pulses is illustrated in Figure 8. These pulses are generated; (a) during one phase loss (b) briefly during abnormal dips of line voltage (c) if the DC bus is short circuited and the SCR firing angle is advanced by more than about 30 from the zero crossing of the line voltage With 1-phase shutdown enabled, generation of "1-phase loss" pulses under condition (b) reinforces the ramp clamp function. Under condition (c) it results in automatic limiting of short circuit current, as explained later. The 1-phase loss pulses at 1PHLED output follow the output of the 1-Phase Loss Circuit. www.irf.com 19
IR1110
ADVANCE INFORMATION
Line Loss Circuit The output of the line loss detection circuit is high in normal operation. If all input phases are lost, it goes low, after a delay, determined by C3PH, which would typically be set to about 2 cycles. When the output of the Line Loss circuit goes low, Q1 is turned OFF. This disconnects RPKD from ground, allowing CPK to hold its charge during the line outage. The output of the line loss circuit feeds via NAND 2 to the LNLSLED output driver. If LNLSSL is connected to VSS, the 1-phase loss pulses are multiplexed with the output of the line loss circuit at the LNLSLED output. If LNLSSL is connected to VDD, the LNLSLED signal signifies loss of all input phase only. Line Voltage Comparator The output of the Line Voltage Comparator is low when VPKLL exceeds a reference value that is set by RLS1 and RLS2. The LNLED output follows the output of the Line Voltage comparator. PWM Control of VBUSREF VBUSREF can be controlled by Pulse Width Modulation (PWM). The IR1110 responds only to the average value of this waveform; suitable PWM frequency is in the range of one to several kHz. Figure 9 shows an opto-coupler circuit for transmitting an isolated PWM input. Control of the ON/OFF duty cycle of the opto-transistor, from 0 to 100%, controls the average value of VBUSREF from VMIN to VMAX, where; R1 VMIN = R1 + R2 R1 VMAX = R1 + R' R2R3 R' = R2 + R3 VSS VSS
The average value of VBUSREF(D) at duty cycle D is: VBUSREF(D) = VMIN + D(VMAX - VMIN) As an example, if VSS = -5.0V, R1 = 7.32k, R2 = 16.9k, R3 = 1.91k, then the average value of VBUSREF will be controlled from approximately -1.5V to -4.0V, corresponding to a range of control of the bus voltage from 37.5% to 100% of the maximum value at maximum operating line voltage. 20 www.irf.com
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IR1110
Dedicated One Phase Operation The IR1110 can be set for dedicated operation of a 1-phase half-controlled SCR bridge. The UIN and VIN input terminals are used. No connection is made to WIN. When Pin 12 is connected to VSS, the W timing wave and watchdog circuits are disabled, the watchdog reset time is optimized for 1-phase operation, and 1-phase shutdown is disabled, regardless of the connection of Pin 13. Snubber Derived Power Supply Snubbers will generally be required, either across the AC lines or directly across the SCRs, to limit dv/dt when the line voltage is switched on. If SCR snubbers are used, the snubber current can be used to derive the power supply voltages for the IR1110 and SCR drivers. With reference to Figure 10, positive snubber current flows via the three RC snubbers and the D+ diodes, to create a nominal 15V supply across ZD1 and C1, for the SCR driver. A nominal positive 5.1V VDD supply is developed across ZD2 and C2. Negative snubber current flows via D- diodes, to create a nominal -5.1V VSS supply across ZD3 and C3. The ZD1 and ZD4 protect the supply voltages against transients on the line voltages. This power supply circuit requires that the average current consumed by the SCR driver circuits does not exceed about 10mA. Note that an auxiliary winding on a DC bus derived switching power supply would not by itself serve the IR1110. This is because bus-derived power cannot deliver voltage until after charging of the DC bus capacitor has already commenced, while the IR1110 must be powered before charging of the bus capacitor commences. It would be possible to use an auxiliary winding on a DC bus derived power supply to supplement the snubber derived power. This could be preferred where the AC input line inductance is high, therefore only minimal snubbers - insufficient to furnish the total power required by the IR1110 and SCR drivers - are needed for dv/dt protection of the SCRs.
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IR1110
ADVANCE INFORMATION
U
V
W
VDD
VDD RLS1 VPKLL SCR VOLTAGE COMPARATOR
VDD
CINTU,V,W RU1 RV1 RW 1 1 UIN RW 2 2 VIN RU2 RV2 3 WIN Line Voltage Processing Circuit 6 3 , 5 9 , 5 5 RINTU,V,W RSTRU,V,W 64,60,56 61,57,53 CINTU,V,W Timing Wave Integrator VPKREC INTNU,V,W 52,53,54
RPKLL2 23 CPKLL RPKLL1 SCRREF 50
RSC1
42 LNSET 39 RLS2 LINE VOLTAGE COMPARATOR LNLED
RSC2 SCR TIMING COMPARATOR 45,46,47 AND1 SCRU,V,W VDD UV COMPARATOR AND2
RPKFIL 34 VPK RPKD 33 CPK
WatchDog
35 36,37,38 WDCAPU,V, W
IRAMP
21
RRAMP
RAMP BUFFER AMP
TIMING WAVE REF SUMMING AMP
20 CRAMP RRAMP
Q3 RAMPERR VRAMP 18 RCLAMP2 19 RAMP ERROR AMP TIMING WAVE INTERSECT COMPARATOR
UVLO COMPARATOR
VDD
CRAMP
Q4
RCLAMP1
RPOS2 RPOS1 RNEG1 6 7 5 VBUSO
AND3 AND4
Q1
1PHASE LOSS CIRCUIT
41 1PHCAP 15 24 1PHLED UVLOCAP CUVLO Q6
DC+ DC-
C1PH
RNEG2
DCREG2 9 BDIP1 29 ERROR AMP 1 (INVERTING) 11 DCREGC 10 RERR ERROR AMP 2 (NON-INVERTING)
3PH/1PH COMPARATOR
1PHEN
LINE LOSS CIRCUIT
C3PH
13 3PHCAP 16
VDD
40 LNLSLED NAND2
INVERTING AMPLIFIER VBREF 8 RDFIL
DCREG1
CERR 14 Q5 LNLSSL
BDIPHLD RDIP1 30 Q2 CHOLD 27 RESET NAND1 VOLTAGE DIP COMPARATOR CBDIP2
BDIP2 RDIP2
DELAY
28
Q2
BDIPCAP CBDIP1
Figure 4 Detailed Functional Block Diagram
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ADVANCE INFORMATION
IR1110
U
V
W
U
V
W U,V,W Timing Waveforms Timing Wave Reference = VP K - V R A M P
U V W SCR Timing Comparator Output
Figure 5 Timing Waveforms, Timing Wave Reference SCR Timing Comparators
DCREG1 PIN 11
DC LOOP GAIN REDUCED BY R1 R2/(R1 + R2) R1 + R2 = 200k ohms approx.
RERR
DCREGC PIN 10
R2
CERR
Figure 6 Circuit for Reducing the DC loop gain www.irf.com 23
IR1110
+12.5 to +15V
ADVANCE INFORMATION
0.0047uF 25V 470 1/16W
C1
5.6K 1/16W
R2
R1 7,8 4 3
SCRU SCRV SCRW
2 1
IRF7509
3 5,6 C2 .1uF 25V 56 1/8W R4 43 1/8W SCR GATE U, V, W
OPTIONAL
Figure 7 SCR Gate Driver Circuit
NORMAL 3-PHASE OPERATION
INPUTs to 3PH/1PH Comparator
<0>
Output of 1-Phase Loss Circuit
(a) LOSS OF ONE INPUT PHASE
INPUTs to 3PH/1PH Comparator
<0>
Output of 1-Phase Loss Circuit
Figure 8, 8(a) Principle of Generation of 1-Phase Loss Pulses 24 www.irf.com
ADVANCE INFORMATION
IR1110
(b) ABNORMAL DIP OF LINE VOLTAGE
INPUTs to 3PH/1PH Comparator
<0>
Output of 1-Phase Loss Circuit
(c) DC BUS SHORT CIRCUIT. FIRING ANGLE 30 ADVANCED
INPUTs to 3PH/1PH Comparator
-
<0>
Output of 1-Phase Loss Circuit
Figure 8(b), 8(c) Principle of Generation of 1-Phase Loss Pulses
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IR1110
ADVANCE INFORMATION
R1 TO VBUSREF PIN8 of IR1110 R3 6 8 2 R2 PWM INPUT 3
HCPL0453
5
VSS
Figure 9 Circuit for PWM Control of DC Bus Voltage
150
1/10W
+12.5 to +15V
220 1/4W
15V 1W 5% DC+
ZD1 100uF
C1 ZD2 1N5231C
ZD5 1N5231C C2 330uF 6.3V C3 330uF 6.3V
+5.1V
ZD4
ZD3 1N5231C 6.8V .5W 5% 75 1/10W
-5.1V
D+ 100 10W .15uF 1200V 480V AC 3-Phase Input U V W
DD+ 100 10W .15uF 1200V DD+ 100 10W .15uF 1200V 1N4004 D-
Note: For 240V input, snubber capacitor = .33uF/600V snubber resistor = 10 2W
DC-
Figure 10 Snubber Derived Power Supply
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ADVANCE INFORMATION
IR1110
SCR Driver Supply
11.0V min
VDD
4.0V
<0>
-4.0V
VSS
AC LINE VOLTAGE
T0 T1
T2
T3
T4
1.0msec < T0 - T1 < 80msec 100msec < T1 - T2 T3 - T4 < 40msec VSS should track VDD within +/-10% during rise/fall time
Note: T4 is the event of Undervoltage Lockout
Figure 11 Power Supply Requirement
LOSS OF LINE SHUTDOWN CIRCUIT R1 27K 5% 1/16W TO LNLSLED (PIN40 IR1110)
LOW LINE SHUTDOWN CIRCUIT D1 1N4148 R2 24K 5% 1/16W
TO UVLOCAP (PIN24 IR1110) TO 1PHLED (PIN41 IR1110) TO LNLED (PIN42 IR1110)
220K 5% 1/16W
Q1 2N4401
Q2 2N4401
47K 5% 1/16W
C1 .1uF
NOTES: (1) If Pin14 to VDD, use CUVLO=.1uF and omit D1,R2 ( 2) I f Pi n14 t o VSS, use CUVLO=. 22 u F a n d o m it C 1 ,D 1 ,R 2 (3) If power supply rise time < 80msec (Figure 11), connect pin 14 to VSS, use CUVLO=.22uF, and omit C1,D1,R2. (4) If Figure 13 circuit is used. Connect pin 14 to VDD. Use CUVLO=0.22uF and R1=0. (5) Set RLS1, RLS2 for LNLED low above 85% of min operating voltage
Figure 12 Loss of Line and Low Line Shutdown Circuits www.irf.com 27
IR1110
ADVANCE INFORMATION
VDD
470K 5% 1/16W 47K 5% 1/16W
R2
R3
NOTE: (1) Remove CERR and RERR (2) Connect PIN10 of IR1110 to GND (3) Set VBUSREF = VLINEMIN X 3.4 VLINEMAX
(4) PIN13 connected to VDD to enable 1-phase shutdown at low bus voltage
TO PIN24 IR1110 Q2 2N4401
R1 TO PIN11 IR1110 (ERROR AMP 1 OUTPUT) 470K 5% 1/16W
Q1 2N4401
.1uF 10%
Figure 13 Circuit for Enabling 1-Phase Shutdown During Ramp-Up, Disabling During Normal Operation (Bus Voltage Control Function Not Used)
To pin6 of IR1110
4.7K 6 8 2 10mA to clamp V RAMP to zero 3 5 HCPL0453
VSS
Figure 14 Circuit for Externally Clamping VRAMP to zero
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ADVANCE INFORMATION
IR1110
VDD
a)
1/2 LM2903
191k 1% 1/16W 100k 5% 1/16W
To PIN20 IR1110 (CRAMP) 120k 5% 1/16W
IRLML2803
To PIN7 IR1110 1M 1% 1/10W Note 1) Use CRAMP = 0.33uF
VSS
VDD
To PIN20 IR1110 (CRAMP)
b)
100k 5% 1/16W 120k 5% 1/16W
2N4401 470k 5% 1/16W To PIN11 IR1110 2N4401 Note 1) Use CRAMP = 0.33uF 2) Remove CERR and RERR 3) Connect PIN10 IR1110 to ground 4) Set VBUSREF = -0.8V
0.1uF 10%
Figure 15 Circuits for reducing tD1FIRE
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IR1110
ADVANCE INFORMATION
Operating Scenarios and Design Options
Power Supply Response Characteristics The UV comparator responds to the amplitude of the VDD supply, to control the ramp clamp. In order to correctly accomplish this function, the power supply should have the response characteristics illustrated in Figure 11, and 1-phase shutdown must be enabled. A minimum rise time of 100msec during initial power-up is required to provide sufficient delay time, before the output of the UV comparator goes high, for VPK to become established before ramp-up commences. During loss of line voltage, VDD should not hold up above 4.0V for more than 40msec, to ensure timely clamping of the ramp via the UV comparator. The snubber derived power supply in Figure 10 has the required rise time, however holdup time exceeds 40msec. Timely clamping of the ramp can instead be accomplished by the external Loss of Line Shutdown circuit, described below. If 1-phase shutdown is disabled, the rise time of VDD must be increased to about 200msec to control the ramp clamping function. In this case it may generally be better to control the ramp clamp via the UVLO comparator, by increasing CUVLO to 0.22uF. The rise time of VDD is no longer critical, and can have a minimum value of 1msec. Loss of Line Shutdown circuits The Loss of Line Shutdown circuit in Figure 12 clamps the ramp during line outage, via the Undervoltage Lockout Comparator. The Note (3) option of Figure 12 also eliminates dependence on a minimum power supply rise time of 80msec. CUVLO is increased to 0.22uF, to provide sufficient delay during power-up, via the UVLO Comparator. The rise time of the power supply is not now critical, and can have a minimum value of 2.0msec. A side effect of increasing CUVLO is to increase the shutdown time when one phase is lost. With Pin 14 connected to VSS, this is corrected by Q1 being turned on during each 1-phase loss pulse, which adds to the discharge current for CUVLO, via R1. Low Line Shutdown circuit The Low Line Shutdown circuit in Figure 12 clamps the ramp and removes the SCR firing pulses if the line voltage falls to less than 85% of the minimum normal operating level. This circuit may not be necessary for all applications, but its inclusion will provide added insurance of correct operation during abnormal low line conditions. Loss of one phase during three phase operation The 1-Phase Shutdown circuit clamps the ramp and removes the SCR firing pulses if one input phase is lost for more than about one cycle. When the missing phase returns, the ramp is unclamped and the bus voltage ramps back to the set value. If 1-Phase Shutdown is disabled, the IR1110 will continue to deliver DC bus voltage when one input phase is lost. A potential problem arises, however, if the bus voltage is being regulated significantly below the maximum value. If one phase is lost and the ramp remains unclamped for more than one or two cycles, when the missing phase returns the bus voltage may transiently jump to almost the maximum possible value, before it is regulated back to the set value. This can www.irf.com 30
ADVANCE INFORMATION
IR1110
result in excessive bus capacitor charging current. For this reason it is recommended that the 1-Phase Shutdown circuit is enabled, (Pin 13 connected to VDD) in designs where the voltage control function of the IR1110 is used. For designs where the voltage control function is not used, operation at full bus voltage, with 1 Phase Shutdown disabled, allows natural transitioning from 3-Phase to 1-Phase operation, and vice versa, without excessive voltage jumps. With 1-Phase Shutdown disabled, however, transient loss of one phase, during the early part of ramp-up, could cause a jump of bus voltage and a high instantaneous bus capacitor charging current, if the missing phase returns before ramp-up has finished, while the instantaneous bus voltage is still low. The likelihood is remote of one phase being lost and then returning during the infrequently occurring first 50 to 100ms window of the initial ramp-up period. Given the improbability of such an event, provided the instantaneous charging current cannot exceed the surge capability of the SCRs, no additional remedy may generally be necessary. The circuit shown in Figure 13 can be used to protect against this unlikely event, if judged necessary. The polarity of the Error Amplifier 1 average output signifies whether the instantaneous bus voltage is above or below a fixed level, set by VBREF. If one phase loss occurs during ramp-up, when the bus voltage is instantaneously below the set level, the output of Error Amplifier 1 is negative, and Q2 is ON, 1-Phase Shutdown is enabled. If one phase loss occurs at instantaneous bus voltage above the set level, Q2 is OFF and the voltage on CUVLO is pulled high by R3, disabling 1-Phase Shutdown. DC bus Short Circuit With a short circuit across the DC bus, the line-to-line voltages collapse to zero at the SCR firing instants, causing the timing waves to terminate prematurely. If a short circuit is present at start up, 1-phase loss pulses start to be generated as the ramp increases, and the firing angle advances by more than about 30. See Figure 8. With 1Phase Shutdown enabled, these pulses set the UV lock comparator and clamp the ramp. The overall result is that the short circuit current is automatically limited to a relatively low pulsatingt level, as the ramp repeatedly tries to increase, then is rest each time the firing angle attempts to advance by more than 30. If a short circuit occurs during normal operation, the bus dip comparator resets the ramp to zero, limiting the short circuit current within less than half cycle. Thereafter, the short circuit current is automatically limited to relatively low pulsating level, as described above. The short circuit condition is signified by 1-phase loss pulses appearing and disappearing, as the ramp increases then resets, accompanied by essentially zero bus voltage. The interval between pulses depends upon CRAMP. If 1-Phase Shutdown is disabled, and a short circuit exists at start up, the ramp increases, advancing the SCR firing angle, until the line fuses blow, or other external action occurs. For
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IR1110
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example, CRAMP could be clamped via an opto-coupler device to limit the short circuit current. If a short circuit occurs during normal operation, the voltage dip comparator resets the ramp, limiting the short circuit current within less than half a cycle. The ramp will then increase again, until the line fuses blow or other action is taken. The short circuit condition is signified by a train of 1-phase loss pulses, accompanied by essentially zero bus voltage.
Externally controlled shutdown of the rectifier The circuit in Figure 14 can be used, if desired, to externally clamp the ramp voltage, hence also the output voltage of the rectifier, to zero.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 322 3331 IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171-0021 Tel: 8133 983 0086 IR HONG KONG: Unit 308, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2803-7380 Data and specifications subject to change without notice. 7/17/2000
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